`timescale 1ns / 1ps
module CAR(
    input wire clk,
    input wire rst_n,
    input wire [2:0] CAR_control,
    (*MAX_FANOUT=10*)input wire [15:0] IR_input,//input from IR
    input wire [7:0] FLAG,//标志位 FLAG[0]=SF,FLAG[1]=ZF
    input wire step_mode,//单步模式
    input wire step,//单步信号
    input wire load_mode_en,//下载模式使能信号
    output reg [6:0] index,//7bit地址给CM
    (*MAX_FANOUT=10*)output reg [1:0] CAR_state//控制信号有效
    );

    wire increment_signal;
    wire init_signal; //归零信号
    wire jump_signal; //跳转到某一步

    wire SF;
    wire ZF;
    assign SF=FLAG[0];
    assign ZF=FLAG[1];
    reg [2:0] CAR_control_reg;
    assign increment_signal = CAR_control_reg[0];
    assign jump_signal = step_mode ? (step&CAR_control_reg[1] ): CAR_control_reg[1];
    assign init_signal = CAR_control_reg[2];
    

    localparam  addr_send= 0,signal_wait=1,signal_recive=2;
    // assign control_signal_en=(CAR_state==signal_recive);
    always@ (posedge clk) begin
        if ((rst_n==0)||(load_mode_en==1)) begin
            CAR_state<=addr_send;
            index<=0;
        end else begin
            case (CAR_state)
                addr_send:begin
                    CAR_state<=signal_wait;
                    if (increment_signal) begin
                        index <= index + 1;
                    end else if (init_signal) begin
                        index <= 0;
                    end else if (jump_signal) begin
                        //根据IR_input的值跳转
                        case (IR_input[15:10])//6位操作码（64条指令）
                            'd01: index <= 'd04; // load x
                            'd02: index <= 'd07; // store x
                            'd03: index <= 'd10; // move rd, rs
                            'd04: index <= 'd11; // move rd, imm
                            'd05: index <= 'd12; // add rd
                            'd06: index <= 'd15; // add imm
                            'd07: index <= 'd18; // sub rd
                            'd08: index <= 'd21; // sub imm
                            'd09: index <= 'd24; // mul rd
                            'd10: index <= 'd27; // mul imm
                            'd11: index <= 'd30; // and rd
                            'd12: index <= 'd33; // and imm
                            'd13: index <= 'd36; // or rd
                            'd14: index <= 'd39; // or imm
                            'd15: index <= 'd42; // not 
                            'd16: index <= 'd44; // shl rd
                            'd17: index <= 'd47; // shl imm
                            'd18: index <= 'd50; // shr rd
                            'd19: index <= 'd53; // shr imm
                            'd20: index <= 'd56; // cmp rd
                            'd21: index <= 'd58; // cmp imm
                            'd22: index <= 'd60; // jmp addr
                            'd23: index <= ZF ? 'd61 : 'd82; // jz addr
                            'd24: index <= ZF ? 'd82: 'd62; // jnz addr//  不满足条件则跳转到空指令
                            'd25: index <= SF ? 'd82 : 'd63; // jg addr
                            'd26: index <= SF ? 'd64 : 'd82; // jng addr
                            'd27: index <= 'd65; // call addr
                            'd28: index <= 'd71; // ret
                            'd29: index <= 'd74; // halt
                            'd30: index <= 'd75; // push rd
                            'd31: index <= 'd79; // pop rd
                        endcase
                    end
                end
                signal_wait:begin
                    CAR_state<=signal_recive;
                end
                signal_recive: begin
                    CAR_state<=addr_send;
                    CAR_control_reg<=CAR_control;
                end
            endcase

        end


    end


endmodule